1. Field of the Invention
This invention relates to a shift register and a liquid crystal display using the same, and more particularly to a shift register and a liquid crystal display using the same that is adaptive for improving picture quality characteristics.
2. Discussion of the Related Art
Generally, a liquid crystal display (LCD) device controls transmittance of light through a liquid crystal layer using an electric field to thereby display a picture. FIG. 1 shows an active matrix LCD device of a related art.
FIG. 1 shows an active matrix LCD device that includes an LCD panel 13 having (m×n) liquid crystal cells Clc arranged in a matrix array, m data lines D1 to Dm and n gate lines G1 to Gn intersecting each other, and thin film transistors (TFT's) provided at intersections thereof. The active matrix LCD device also includes a data driving circuit 11 for applying video data signals to the data lines D1 to Dm of the LCD panel 13 and a gate driving circuit 12 for applying a scanning pulse to the gate lines G1 to Gn.
The LCD panel 13 has liquid crystal molecules injected between two glass substrates. The data lines D1 to Dm and the gate lines G1 to Gn are provided at the lower glass substrate of the LCD panel 13 and perpendicularly cross each other. The TFT provided at each intersection between the data lines D1 to Dm and the gate lines G1 to Gn applies a data voltage supplied via the data lines D1 to Dn to the liquid crystal cell Clc in response to a scanning pulse from the gate line G1 to Gn. In particular, the gate electrode of the TFT is connected to one of the gate lines G1 to Gn while the drain electrode thereof is connected to one of the data lines D1 to Dm. Further, the source electrode of the TFT is connected to a pixel electrode of the liquid crystal cell Clc. The upper glass substrate of the LCD panel 13 is provided with black matrices, color filters, and common electrodes (not shown). A polarizer (not shown) having a perpendicular light axis is attached onto the upper and lower glass substrates of the LCD panel 13, and an alignment film (not shown) for establishing a free-tilt angle of the liquid crystal is provided at the inner side thereof tangent to the liquid crystal. Each liquid crystal cell Clc of the LCD panel 13 is provided with a storage capacitor Cst. The storage capacitor Cst is provided between the pixel electrode of the liquid crystal cell Clc and the pre-stage gate line or between the pixel electrode of the liquid crystal cell Clc and a common electrode line (not shown), thereby constantly maintaining a voltage of the liquid crystal cell Clc.
The data driving circuit 11 includes a plurality of data driving integrated circuits (ICs), each data driving IC including a shift register, a latch, a digital-to-analog (D/A) converter, and an output buffer. The data driving circuit 11 latches a digital video data and converts the digital video data into an analog gamma compensation voltage to thereby apply them to the data lines D1 to Dm.
The gate driving circuit 12 includes a plurality of gate driving ICs, each of which includes a shift register for sequentially shifting a start pulse every one horizontal period to generate a scanning pulse, a level shifter for converting an output signal of the shift register into a swing width suitable for driving the liquid crystal cell Clc, and an output buffer connected between the level shifter and one of the gate lines G1 to Gn. The gate driving circuit 12 sequentially applies the scanning pulse to the gate lines G1 to Gn to select a horizontal line of the LCD panel 13 supplied with data.
FIG. 2 shows a block diagram of the shift register shown in FIG. 1. In FIG. 2, the shift register is comprised of n stages S_1 to S_n connected in a cascading fashion. A level shifter and an output buffer (not shown) are provided between each of the stages S_1 to S_n and their corresponding gate lines G1 to Gn. A start pulse Vst is input to the first stage S_1 while each of the stages S_2 to S_n receives the output signal of its previous stage (i.e., one of Vg_1 to Vg_n−1) as the start pulse. Further, each of the stages S_1 to S_n has the same circuit configuration and shifts the start pulse Vst or one of the output signals Vg_1 to Vg_n−1 of the previous stages in response to two of four clock signals C1 to C4, thereby generating a scanning pulse having a pulse width of one horizontal period.
FIG. 3 shows an equivalent circuit of a unit pixel including the liquid crystal cell Clc in the LCD panel 13 of the related art. In FIG. 3, “Cgs” represents a parasitic capacitance between the gate and the source of the TFT, “Cgd” represents a parasitic capacitance between the gate and the drain thereof, and “Cds” represents a parasitic capacitance between the drain and the source thereof. Further, “Clc” represents a liquid crystal cell and “Cst” represents a storage capacitor for keeping a voltage of the liquid crystal cell Clc.
FIG. 4 shows a driving signal of the LCD panel 13 based on a SVGA type display. In FIG. 4, “Vd” represents a data voltage output by the data driving circuit 11 to be applied to the data lines D1 to Dm, “Vd+” represents a positive data voltage, and “Vd−” represents a negative data voltage. Further, “Vlc” represents a data voltage charged and discharged at the liquid crystal cell, “Vg” represents a scanning pulse generated at one horizontal period, and “Vcom” represents a common voltage applied to the common electrode of the liquid crystal cell Clc.
As illustrated in FIG. 4, a shift in the data voltage ΔV caused by a kick back voltage or a feed through voltage is generated in the driving signal. ΔV generates a residual image caused by an offset DC voltage as well as flicker caused by periodically changing brightness of the display picture. The ΔV is defined by the following equation:
                              Δ          ⁢                                          ⁢          V                =                              Cgd                          Cgd              +              Clc              +              Cst                                ⁢                      (                          Vgh              -              Vgl                        )                                              (        1        )            As can be seen from the equation, the ΔV is in proportion to a difference between a gate high voltage Vgh and a gate low voltage Vgl.